A Memory-Based Logic Block with Optimized-for-Read SRAM for Energy-efficient Reconfigurable Computing Fabric

A memory-based logic block (MLB), a building block for memory based reconfigurable computing framework, is presented in 130nm CMOS. The MLB is designed with an optimized-for-read (OFR) 6-T SRAM based lookup-table (LUT) and demonstrates single and multi-cycle evaluation of complex functions. Power-aware mapping leverages the data-dependent read power of the OFR SRAM to reduce MLB evaluation power.