A Filtering Mechanism to Reduce Network Bandwidth Utilization of Transaction Execution.

Hardware Transactional Memory (HTM) relies heavily on the on-chip network for intertransaction communication. However, the network bandwidth utilization of transactions has been largely neglected in HTM designs. In this work, we propose a cost model to analyze network bandwidth in transaction execution. The cost model identifies a set of key factors that can be optimized through system design to reduce the communication cost of HTM. Based on the model and network traffic characterization of a representative HTM design, we identify a huge source of superfluous traffic due to failed requests in transaction conflicts. As observed in a spectrum of workloads, 39p of the transactional requests fail due to conflicts, which renders 58p of the transactional network traffic futile. To combat this pathology, a novel in-network filtering mechanism is proposed. The on-chip router is augmented to predict conflicts among transactions and proactively filter out those requests that have a high probability to fail. Experimental results show the proposed mechanism reduces total network traffic by 24p on average for a set of high-contention TM applications, thereby reducing energy consumption by an average of 24p. Meanwhile, the contention in the coherence directory is reduced by 68p, on average. These improvements are achieved with only 5p area added to a conventional on-chip router design.