Model checking of finite-state machine-based scenario-aware dataflow using timed automata

10th IEEE International Symposium on Industrial Embedded Systems (SIES)(2015)

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摘要
Dataflow formalisms are widely used for modeling and analyzing streaming applications. An important distinction is between static and dynamic formalisms, the latter allowing for the workload to change on-the-fly. The recently introduced finite-state machine based scenario aware dataflow (FSM-SADF) is a dynamic dataflow formalism that increases the expressiveness of the static synchronous dataflow (SDF) formalism, by allowing finite-state control, while to a large extent retaining its design-time analyzability. This paper reports on the translation of the FSM-SADF formalism to UPPAAL timed automata that enables a more general verification than currently supported by existing tools. We base our translation on a compositional approach where the input FSM-SADF model is represented as a parallel composition of its integral components modeled as automata. Thereafter, we show how to model check quantitative and qualitative properties both supported and not supported by the existing tools. We demonstrate our approach on a realistic case study from the multimedia domain.
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关键词
model checking,streaming application analysis,scenario aware dataflow,finite-state machine-based scenario aware dataflow,dynamic dataflow formalism,static synchronous dataflow formalism,SDF formalism,finite-state control,UPPAAL timed automata,FSM-SADF model,parallel composition
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