A Framework for Multi-Fpga Interconnection Using Multi Gigabit Transceivers

In this paper we present an interconnect framework for FP-GAs based on multi gigabit transceivers (MGTs), typically available in modern reconfigurable devices. The framework provides higher bandwidth while using fewer pins compared to existing approaches based on ordinary FPGA IO pins. Unlike other implementations using MGTs for device interconnection, special care has been taken to achieve high throughput and data integrity while keeping latency, resource usage and protocol overhead very low. From a designers perspective, the introduced FPGA interconnect is used like an ordinary asynchronous FIFO allowing easy integration into existing digital designs with no or only very little modification. Depending on the available MGTs, the bandwidth per connection reaches from 3.125 to 28 GBit/s allowing large amounts of data to be moved quickly between multiple FPGAs. The framework allows the use of optical fibers for the data links. This enables an easy distribution of FPGA networks over hundreds of meters. Thus, the presented approach is not only applicable for multi-FPGA prototyping of complex novel computing architectures but also for large data processing facilities commonly found e.g. nearby detectors of large particle accelerator experiments.