Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reduction

We describe design techniques, calibration method, and measurement results of an all-digital temperature sensor in 28 nm CMOS. To deal with the issue of Vcc being near the zero-temperature-coefficient point, a new delay cell with much improved temperature sensitivity is proposed. Adaptive 1-point (1P) calibration is proposed to reduce the serious impact due to process variations, while without increasing the calibration cost. Measurement results show that, compared to the conventional 1P calibration, the new method achieves a 32% error reduction.