Reconfıgurable and selectively-adaptive signal processing for multi-mode wireless communication

A selectively-adaptive and configurable 8–72 tap distributed arithmetic FIR filter consuming 0.016mm2 total area in 22nm CMOS with a companion RLS-based adaptation hardware accelerator for large scale signal processing in communication systems is presented. Overhead of duplicate LUTs in partial-parallel implementations is avoided by using multi-port memories to achieve required application throughputs and memory footprint is optimally reduced by systematically trading logic for memory. The first SoC implementation of a serialized RLS-based adaptation hardware accelerator that adapts the filter coefficients on an as-needed basis consumes 0.089mm2 total area at an estimated total power of 12.5mW at 0.8V supply.