JSRAM: A Circuit-Level Technique for Trading-Off Robustness and Capacity in Cache Memories

In this paper, we propose Joint SRAM (JSRAM) cell, a novel circuit-level hardening solution for having a flexible trade-off between cache capacity and reliability. Our solution aims at addressing both permanent and transient faults in SRAM cells. JSRAM technique enhances read-stability by increasing critical Read Static Noise Margin (RSNM) to decrease faults when circuit operates at lower VDD voltages, while improving yield. It also increases hold-stability to mitigate against soft-errors, due to noise or radiation when circuit works in harsh environmental conditions. Moreover, our approach is resistant to Multi Bit Upsets (MBUs) while it is fully immune against single faults due to a novel self-correcting technique. Specifically in fault prone condition, some user pre-selected cache lines and ways are combined together vertically and horizontally at circuit level to form more robust cache cells. Four cells are joined by joiner circuits to form one robust cell. Joining cells can be selected far enough to cope with MBUs. In the case of soft-errors, this technique can be interpreted as virtually doubling transistor size. In the case of permanent faults, it can be seen as increasing β ratio to improve readability. This approach provides versatile and flexible solution with negligible performance penalty and low area overhead. This technique requires one extra transistor per cell for joiner circuit. However, extra transistor is only involved in the reliable mode. Therefore it can be described as 6T+1T SRAM cell. While our implementation is on 6T SRAM with 22nm technology, it is applicable to other SRAM structures and technologies.