18.4 An 1.1V 68.2GB/s 8Gb Wide-IO2 DRAM with non-contact microbump I/O test scheme.

The emergence of the internet of everything (IoE) demands high-performance, real-time multi-media and wideband networking in battery-operated mobile systems. For this reason, higher bandwidth and lower power mobile DRAMs are becoming increasingly critical. As promising candidates of next-generation mobile DRAM, the development of LPDDR4 [1] and wide-IO2 (WIO2) DRAM is ongoing these days. The conventional single data rate (SDR) wide IO DRAM [2] has achieved ×4 data bandwidth compared to LPDDR2 by increasing the number of IOs (e.g. 512 DQs). The WIO2 DRAM in this paper has 512 DQs, which is the same as SDR wide-IO DRAM, but by using double data rate (DDR) and operating at 1066Mb/s, its bandwidth achieves 68.2GB/s, which is quadrupled compared to LPDDR4 (single-die comparison). Moreover, since WIO2 DRAM is stacked in a 3D structure with the DRAM controller (system-in-package type), the input/output capacitance (CIO) is decreased and a power efficiency of 28mW/GB/s in READ operation mode is achieved.