27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS.

2016 IEEE International Solid-State Circuits Conference (ISSCC)(2016)

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In recent years, we have seen the emergence of multi-GS/s medium-to-high-resolution ADCs. Presently, SAR ADCs dominate low-speed applications and time-interleaved SARs are becoming increasingly popular for high-speed ADCs [1,2]. However the SAR architecture faces two key problems in simultaneously achieving multi-GS/s sample rates and high resolution: (1) the fundamental trade-off of comparator noise and speed is limiting the speed of single-channel SARs, and (2) highly time-interleaved ADCs introduce complex lane-to-lane mismatches that are difficult to calibrate with high accuracy. Therefore, pipelined [3] and pipelined-SAR [4] remain the most common architectural choices for high-speed high-resolution ADCs. In this work, a pipelined ADC achieves 4GS/s sample rate, using a 4-step capacitor and amplifier-sharing front-end MDAC architecture with 4-way sampling to reduce noise, distortion and power, while overcoming common issues for SHA-less ADCs.
pipelined ADC,CMOS,medium-to-high-resolution ADC,SAR ADC,time-interleaved SAR,SAR architecture,comparator noise,complex lane-to-lane mismatches,pipelined-SAR,high-speed high-resolution ADC,4-step capacitor,amplifier-sharing front-end MDAC architecture,4-way sampling,word length 13 bit,size 16 nm
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