Phase Shift Keying Demodulator With Decision Feedback Phase-Locked Loop

This paper proposes a phase shift keying (PSK) demodulator with a decision feedback phase-locked loop. It shrinks the size of capacitor without its performance degrade, compared to that of the conventional PSK phase-locked loop. When a certain threshold is reached by a decision summation, the negative feedback on the loop filter's control voltage is provided. Modeled and simulated in VerilogA, the working speed of the proposed circuit is up to 27.12 Mbps, and it can operate for an infinite period of time with the reduced size of the capacitor.