Tracking BTI and HCI effects at circuit-level in adaptive systems

This work proposes a new method for measuring the performance loss of a processor due to aging (BTI and HCI). It is designed for any adaptive system incorporating in-situ delay monitors and local temperature sensors. To validate it, we developed a simplified circuit-level model for BTI/HCI effects in 28nm FD-SOI technology with a relative small error (<;1%). The correct operation of the proposed method has been verified in MATLAB/Simulink environment. It is shown that one can measure the circuit aging over a wide range of temperatures, the circuit aging being determined by the reduction of the maximum clock frequency.