An 18 µW spur canceled clock generator for recovering receiver sensitivity in wireless SoCs

Yosuke Ogasawara,Hiroki Sakurai,Ryuichi Fujimoto,Kenichi Sami

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)（2016）

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摘要

A novel spur canceled clock generator (SCCG) capable of recovering RX sensitivity degradations caused by digital clocks in wireless SoCs is presented. Clock spurs which degrade RX sensitivity are canceled by applying the SCCG to the digital circuits or ADCs. The SCCG is integrated into a Bluetooth ^® smart SoC fabricated in a 65 nm CMOS process. Measured clock spur reduction of over 35 dB and RX sensitivity recovery of 4 dB are achieved. The power consumption and occupied area of the SCCG are only 18 μW and 40 μm × 120 μm, respectively.

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关键词

spur canceled clock generator,SCCG,receiver sensitivity,system-on-chip,wireless SoC,RX sensitivity degradations,digital clocks,digital circuits,ADC,Bluetooth smart SoC,CMOS process,clock spur reduction,RX sensitivity recovery,power consumption,power 18 muW,size 65 nm,size 40 mum,size 120 mum

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