Computational Architecture for Fast Seismic Data Transmission between CPU and FPGA by Using Data Compression

We aim to use a data compression strategy to improve the seismic data transfer between CPU and FPGA through the PCIe bus. In order to improve the transfer speed, it is necessary that the compressed data transfer time (t ₁ ) plus the decompression time (t ₂ ) has to be less than the traditional transfer time (t _t ), that is t ₁ + t ₂ <; t _t . Otherwise, the strategy will not improve the transfer speed. We calculated the speed-up in the transfer speed by speed up = t _t /(t ₁ + t ₂ ).