Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.

Aibin Yan,Zhengfeng Huang,Maoxiang Yi,Xiumin Xu,Yiming Ouyang,Huaguo Liang

IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2017）

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摘要

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-...

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关键词

Latches,Feedback loop,Inverters,Radiation hardening (electronics),Robustness,Power dissipation,Integrated circuit interconnections

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