Software-Hardware Codesign for Efficient Neural Network Acceleration.

IEEE Micro(2017)

引用 84|浏览121
暂无评分
摘要
Designers making deep learning computing more efficient cannot rely solely on hardware. Incorporating software-optimization techniques such as model compression leads to significant power savings and performance improvement. This article provides an overview of DeePhi's technology flow, including compression, compilation, and hardware acceleration. Two accelerators, named Aristotle and Descartes, ...
更多
查看译文
关键词
Hardware,Neural networks,Machine learning,Deep learning,Field programmable gate arrays,Computer architecture,Two dimensional displays
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要