Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders

This paper proposes a layered decoder architecture for array QC-LDPC codes which targets tens of Gbps data rates. It relies on layer unrolling with pipeline stages in between layers, allowing simultaneous decoding of multiple layers. The most important features of the proposed decoder are: (i) fully parallel processing units within each layer (ii) hardwired layer interconnect that allows the removal of high cost variable shift units, (iii) A posteriori log-likelihood ratio (AP-LLR) message memory type of storage is replaced by in-between layers pipeline registers, as the messages are being forwarded from one layer to the next. Data dependencies is this masively parallel structure is resolved by decoding multi-codewords at time. Hence, the proposed architecture allows optimum throughput/cost ratio. FPGA based implementation results indicate that for a 1296 bits LDPC code with 3 layers, throughput of up to 62 Gbps for an average of 4 iterations is by obtained using the proposed architecture.