A 2.4mW, 111dB SNR continuous-time ΣΔ ADC with a three-level DEM technique

This paper presents a multi-bit continuous-time sigma-delta (ΣΔ) audio ADC employing 3-level unit-elements with 1 ^st -order mismatch shaping. An input common-mode (CM) stabilization circuit is used to accommodate a 7 V common-mode voltage range when DC coupled. The converter uses a tuning technique which allows a wide range of clock speed, RC variation while mitigates the inter-symbol interference and clock jitter sensitivity issues in the feedback current steering DAC. The ADC achieves 111 dB A-weighted SNR, -98 dB THD+N in the 22 kHz bandwidth, while consumes a total of 2.4 mW from a 3.3 V supply, and occupies ~0.5 mm ² in a 0.18 um CMOS process.