A Background Calibrated 28gs/S 8b Interleaved Sar Adc In 28nm Cmos

A 28-GSIs timeinterleaved ADC suitable for PAM4 optical and backplane applications is presented. The architecture uses a tworank 2x(4:4) sampling network to interleave 32 81) SAR ADCs employing redundancy to relax DAC settling requirements. A DSP core estimates and corrects the gain, offset and timing error between channels. An ENOB of 5.8b and 5.4b is achieved with I-Cflz and 13.36Hz input signals. The ADC consumes 165-mW from a single 950mV power supply and is fabricated in a 28nm CMOS process occupying 0.24mm(2).