Modeling the Data Flow Application Specific Integrated Circuit with SystemC.

The data flow computation is friendly to parallel processing. However, modeling of an asynchronous data flow processor in very-large-scale-integrated-circuit (VLSI) design often needs specific tools. This paper will propose a data flow architecture and a modeling method that uses common describe language-SystemC. The proposed architecture is composed of some similar units, called hold-match-fetch components. The model involves SystemC models of tokens, channels, operation units and hold-match-fetch components. The architecture and modeling method were used in a data flow advanced-encryption-standard (AES) application-specified-integrated-circuit (ASIC) implementation successfully.