Impact Of Tsv Integration On 14nm Finfet Device Performance

The integration of Through-Silicon Vias (TSVs) in CMOS wafers has the potential to cause performance shifts of devices in close proximity due to mobility change caused by mechanical stress. To ensure successful integration of TSV into a baseline technology, these shifts must be negligible to allow seamless integration of TSVs into circuit designs. As the first publication of its kind by an advanced node foundry, this paper presents results of a study to analyze TSV impact on 14nm FinFET device and analog circuit performance. These include n or p type short and long channel FETs, current mirrors, and operational amplifiers (op-amp). The unique TSV capture pad structure used by GLOBALFOUNDRIES for advanced node TSV integration is discussed. This structure allows for improved TSV middle integration yield and ensures that a good electrical connection from the back-end of line (BEOL) to the TSV is formed. A physical property analysis was also done on the TSV structure to determine capacitance, leakage, and dielectric liner breakdown voltage. Finally, a full suite of characterization measurements were performed on the 14nm FinFET thin wafers to assess the impact of the wafer thinning process on front-end of line (FEOL) devices.