Study Of Mosfet Thermal Stability With Tsv In Operation Temperature Using Novel 3d-Lsi Stress Analysis

A large thermal-mechanical stress caused by the mismatch of thermal expansion coefficients (CTEs) between the copper and silicon substrate occurs in the active area of the stacked 3D device using the through-silicon via (TSV). Therefore, the study of TSV-induced stress is of fundamental importance in our understanding of the keep-out zone (KOZ). We investigated the metal oxide semiconductor field-effect transistor (MOSFET) thermal stability of a device operated by combining Technology Computer-Aided Design - Simulation Program with Integrated Circuit Emphasis (TCAD-SPICE) stress analysis and an actual ring oscillator circuit (ROSC) nearby TSVs. The MOSFET drain current (Id) fluctuates in response to the behavior of the Si stress caused by the TSVs. However, it was found that the simulation and test measurement results showed that the KOZ becomes smaller because the electric charge/discharge is canceled in the case of a p/n MOS inverter circuit. This study showed the importance of the design of the KOZ, which includes the temperature fluctuation phenomenon in a real integrated circuit device operation.