Reduced Complexity Many-Core: Timing Predictability Due to Message-Passing.
ARCS(2017)
摘要
The Reduced Complexity Many-Core architecture (RC/MC) targets to simplify timing analysis by increasing the predictability of all components. Since shared memory interference is a major source of pessimism in many-core systems, fine-grained message passing between small cores with private memories is used instead of a global shared memory.
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