At-Speed Capture Global Noise Reduction & Low-Power Memory Test Architecture

Traditionally, DFT patterns exacerbate dynamic power consumption in large ASICs. At-speed scan and memory tests are sensitive to voltage droop and peak current because the power grid is designed for functional power viruses (maximum workload applications) whose power consumption is much lower than DFT patterns. Our goal in this work is to ensure that the quality of test is not compromised while power is constrained to be within sign-off power budgets. We present an IEEE 1500-compliant Global Low Power Capture (GLPC) architecture with minimized interconnects between sub-blocks. For memory tests, we also present an extension of the architecture, Low Power MBIST (LP-MBIST) which shuts down the toggling of logic flops. Experimental results for both architectures show appreciable dynamic power reduction on recently taped out 16nm ASIC chips.