Low-level implementation of the SISC protocol for thread-level speculation on a multi-core architecture.

Milan B. Radulovic,Sylvain Girbal,Milo Tomasevic

Parallel Computing（2017）

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摘要

•A low-level implementation and evaluation of the SISC WI TLS protocol.•The modification of existing and adding the new components to support TLS.•The overhead evaluation in term of cache cycle latency, area, and power costs.•No particular issues identified with regards to cache latency.•TLS has a significant impact in term of overhead on area and power.

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关键词

Chip multiprocessors,Thread-level speculation,Memory communication,Speculative and coherence protocols,Simulation,Low-level implementation

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