A 90nm Fpga I/O Buffer Design With 1.6gbps Data Rate For Source-Synchronous System And 300mhz Clock Rate For External Memory Interface

As FPGAs become more integrated into high-speed systems, high performance I/O with excellent signal integrity becomes more important. This paper describes how these challenges were met on an FPGA developed to support 1.6Gbps differential source-synchronous standards and 30OMHz external memory interfaces. The I/O buffer features programmable drive strength, output impedance matching, hot-socketing compliance, and 3.3v tolerance. High-speed performance was achieved using design techniques of differential level-shifters with voltage and temperature compensated current sources, on-chip decoupling capacitors, and floating-well output buffers. In addition, DLLs and programmable phase offset circuits were used to obtain precise timing control. The chip was manufactured on a 90nm CMOS process.