Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs

Haipeng Zha
Haipeng Zha
Vaishnavi Sahir
Vaishnavi Sahir
Huimei Cheng
Huimei Cheng

ASYNC, pp. 85-93, 2017.

Cited by: 1|Views7
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Abstract:

Both ring-oscillator based clocks and bundled-data designs mitigate the ill effects of process, voltage, and temperature (PVT) variations. They both rely on delay lines which, when made post-silicon tunable, offer the opportunity to add test margin into the design in which the delay line in shipped products is set slower than that which i...More

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