Design of robust pseudo-resistors with optimized frequency response

In this paper, the implementation of very large time constant circuits by means of MOS-bipolar pseudo-resistors (PR's) is addressed. Three main aspects regarding the design of a PR are discussed: (i) operating voltage range and linearity, (ii) precision and robustness against process, voltage, and temperature (PVT) variations and (iii) frequency response degradation. A bias voltage source for precisely tuning PR's and reducing its sensitivity to PVT variations while maintaining good operating voltage range and frequency response is proposed. Monte Carlo simulations using a standard 0.35 μm CMOS process in Cadence show that the proposed bias voltage source reduces the σ/μ ratio of PR's from 1.5 to 0.4. With the bias circuit and the design approach proposed, PR's with an equivalent resistance up to dozens GΩ and THD below 3% can be obtained for signal amplitudes below 150 mV and frequencies from DC up to 8 kHz.