A pipeline hog feature extraction for real-time pedestrian detection on FPGA.

Pedestrian detection is a vital function of the emerging autonomous vehicle industry. HOG is widely used as the feature extractor for pedestrian detection thanks to its high accuracy despite the fact that it is computationally expensive. Hardware accelerators using GPUs or FPGAs are used in several proposals to address its real-time execution. There is always a trade-off between real-time processing, energy efficiency and accuracy in the existing solutions. In this paper, we present a pipelined implementation of HOG feature extraction on a low-cost Cyclone V SoC FPGA platform. The design is provides a latency of 4ms for every 640x480 input frame, which corresponds to 250fps. The whole detection system reduces the power consumption by 53.3% and 96% compared with state of the art FPGA and GPU alternatives.