An Area Efficient Low Power ECoG Front-End Chip for Digitalized Subdural Grid

An area efficient and low power electrocorticogram (ECoG) front-end chip for digitalized subdural grid is proposed in this paper, which consists of 64 front-end recording channels, 8 10-bit ADCs, one SRAM buffer, internal oscillator and bandgap reference. Each front-end recording channel achieves a gain of 60dB, a power dissipation of 16.18 μW, and integrated input-referred noise of 1.34μV in the range of 1Hz to 300Hz. The integrated 10-bit SAR ADC achieves A/D conversion on chip, decreasing the number of transmission lines with improved anti-interference ability.