An 8-Gb 12-Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications.

IEEE Journal of Solid-State Circuits(2018)

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摘要
The graphic DRAM interface standard GDDR5X is developed as an evolutionary extension to the widely available GDDR5. The implementation presented here achieves a data rate of 12 Gb/s/pin on a single-ended signaling interface with 32 IOs for a total memory bandwidth of 48 GB/s. The GDDR5X DRAM relies on the quad data rate operation enabled by a phase-locked loop (PLL), a receiver with a pre-amplifie...
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关键词
Clocks,Random access memory,Phase locked loops,Receivers,Graphics,Bandwidth,Inverters
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