Comparing Synchronous, Mesochronous and Asynchronous NoCs for GALS Based MPSoCs

In large-scaled Multiprocessor System-on-Chips (MPSoCs) the Globally Asynchronous Locally Synchronous (GALS) design paradigm is widely-used to minimize power consumption. Especially Network-on-Chips (NoCs) utilize several GALS approaches to connect hundreds of CPU cores on a single chip. However, improvements in modern design tools, like the clock concurrent optimization flow (CCOpt-flow), require to rethink the benefit of these GALS-based approach. Therefore, the main focus of this work is the comparison of a synchronous (using CCOpt-flow), a multi-synchronous (mesochronous) and a fully asynchronous NoC design for the usage in hierarchical MPSoCs. In hierarchical MPSoCs multiple CPU cores are tightly coupled to clusters, which in turn are connected via a NoC. As a result, wire length for establishing NoC links between the clusters increases, making a NoC design more challenging. Implementation results for a 28nm FD-SOI standard cell technology have shown that the CCOpt-flow still allows to scale a fully synchronous MPSoCs, with slight drawbacks in maximum clock frequency. Nevertheless, the asynchronous NoC outperforms the other two approaches with respect to performance, power and area requirements. The asynchronous NoC leads to a 3:1% smaller MPSoC design. In addition, the proposed asynchronous NoC router consumes only 53% of the power of a mesochronous router during active communication.