Implementation Of Stable Pufs Using Gate Oxide Breakdown

Instability has been an Achilles heel for physical unclonable functions (PUF) requiring complex error correction or other stability enhancement approaches. This instability originates from parametric nature of variations leveraged as a source of randomness. We develop highly stable PUFs using two random gate oxide breakdown mechanisms: plasma induced damage during semiconductor manufacturing and voltage stressed damage post manufacturing. These gate oxide breakdown PUFs can be easily implemented in commercial silicon processes without extra cost on PUF manufacturing and design, and they are stable and resistant to physical attacks. We fabricated bit generation units for the stable PUFs on 99 testchips with 65nm CMOS bulk technology. Measurement results show that the plasma induced breakdown can generate completely stable responses for all 2871 bits and significant area reduction compared with SRAM PUF can be achieved by eliminating the error correction code (ECC) hardware implementation. For the voltage stressed breakdown, the area cost is further reduced, and its 0.12% bit error rate at a worst case corner can be effectively accommodated by taking the majority vote from multiple measurements without ECC. We show that the responses of gate oxide breakdown PUFs are unique. In addition, we analyze the data of our testchips and show through various statistical distance measures that the bits of our fabricated PUFs are independent.