谷歌浏览器插件
订阅小程序
在清言上使用

Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu

2018 IEEE 13TH INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS (SIES)(2018)

引用 0|浏览7
暂无评分
摘要
High-Ievel synthesis promises a boost in productivity by enabling synthesis of low-level electronic circuit descriptions out of high-level source code. In this work-in-progress paper we present a preliminary evaluation of two freely available high-level synthesis tools using four case studies. We describe the steps required in order to obtain a synthesizable FPGA design from C source code for each use case and discuss the performance of the resulting hardware implementations.
更多
查看译文
关键词
Design methodology,High level synthesis,Hardware description languages,Field programmable gate arrays
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要