Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu
2018 IEEE 13TH INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS (SIES)(2018)
摘要
High-Ievel synthesis promises a boost in productivity by enabling synthesis of low-level electronic circuit descriptions out of high-level source code. In this work-in-progress paper we present a preliminary evaluation of two freely available high-level synthesis tools using four case studies. We describe the steps required in order to obtain a synthesizable FPGA design from C source code for each use case and discuss the performance of the resulting hardware implementations.
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关键词
Design methodology,High level synthesis,Hardware description languages,Field programmable gate arrays
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