A Retrospective View On The Technology Evolution To Support Low Power Mobile Application

In the pursuit of technology scaling, the semiconductor industry has faced steep challenges in meeting low power targets for mobile application. While the voltage scaling has been slowed down beyond 45 nm technologies, industry has managed to enable alternate means for continued scaling of power delay product over technology generations. These include the evolution of process level improvements and device structure engineering as well as the circuit and architecture level innovation. In this paper, we review key technology elements that have contributed to the continued scaling of power for mobile applications while meeting the ever growing demands for performance (throughput). We will discuss the impact of process elements such as high-K- metal gate, low-K spacer, SiGe stress, etc. as well as the device structure engineering from a planar device to FinFET and FDSOI to the overall device electrostatics and their scalability. We will also discuss the effect of design technology co-optimization (DTCO) in achieving PPA (power performance and area) scaling targets in advanced technology nodes. Further, we will review fundamental design IP like SRAM (static random access memory) in advanced technology nodes.