Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window

In this paper, we present a low voltage current limiter that can effectively confine the filament size by limiting the write current to a preset compliance level after forming or SET operations. In addition, a word-line (WL) location-aware and a temperature compensation schemes are also proposed to deal with the ambient variations and tighten cell current distribution. As a result, the silicon data measured from a 36Mb of RRAM test chip demonstrates a 9.5uA of read window after 10K cycles and 85C 10 years of retention test in 40nm logic process.