A High Speed Asynchronous Multi Input Pipeline for Compaction and Transfer of Parallel SIMD Data
2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)(2018)
摘要
Image sensors with programmable, highly parallel signal processing, so called Vision-Systems-on-Chip, perform computationally intensive tasks directly on the sensor itself. Therefore it is possible to limit the amount of output data to relevant image features only. Reading out such features presents a major challenge, since the position and number of features often is not known. Conventional synchronous buses as well as special event-based readout paths are unsuitable for such a system, since both continuous data, e.g. complete images, and sparse data, like feature coordinates, have to be transferred. A readout path based on an asynchronous pipeline is presented, which supports both readout modes with high speed. Furthermore, a method is introduced that, by serialization, allows for arbitrary data word widths without storing any control information within the data stream. The developed circuit components were measured on a proof-of-concept test chip in a 180 nm CMOS technology and were compared with implementations of asynchronous pipelines found in literature. In addition, the use of the pipeline in a Vision- System-on-Chip, which is still in production, is demonstrated.
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关键词
asynchronous pipeline,SIMD,sparse data,low latency,high speed,Vision-System-on-Chip,VSoC
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