An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization

IEEE Journal of Solid-State Circuits(2019)

Cited 23|Views204
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Graphics workloads make highly dynamic use of resources such as execution units (EUs), and thus can benefit from fast, fine-grain dynamic voltage and frequency scaling (DVFS) and retentive sleep. This paper presents a 14-nm graphics processing unit (GPU) prototype with modified EUs which include an integrated voltage regulator (IVR). The IVR enables energy-efficient EU turbo operation, data retention, and $V_{\text {MIN}}$ optimization per EU. Silicon measurements show that IVR-enabled EU turbo operation offers up to 32% (average 29%) energy reduction at constant performance.
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Key words
Graphics processing units,Clocks,Prototypes,Optimization,Voltage control,Dynamic scheduling,Media
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