Evaluation of the system-level SER performance of gigabit ethernet transceiver devices

System-level SER measurements were conducted on two Gigabit Ethernet transceiver devices designed in 28-nm CMOS process to evaluate the true impact of soft error upsets. Measurement results are compared with the system SER estimates based on test chip data for memory and flip-flop SER. Results indicate that most SEUs cause packet errors which are recoverable while the SER for more severe link-drop type events is significantly lower than estimates.