Design and Optimization of Inductive-Coupling Links for 3-D-ICs

Recent research in the field of 3-D system integration has looked to the use of inductive-coupling links (ICLs) to provide vertical connectivity without incurring the inflated fabrication and testing costs associated with through-silicon vias. For power-efficient ICL design, optimization of the utilized physical inductor geometries is essential, but currently must be performed manually in a process that can take several hours. As a result, the generation of optimized inductor designs poses a significant challenge. In this paper, we address this challenge in three main contributions: 1) a novel, nonuniform planar inductor layout that exhibits enhanced performance when compared with conventional uniform inductors; 2) a rapid solver for evaluating inductor layouts; and 3) a high-speed optimization algorithm for determining best performing coil pairs. These three contributions are combined as a CAD tool for optimization of ICLs for 3-D-ICs (COIL-3-D). Results demonstrate that COIL-3-D achieves an average accuracy within 7.8% of finite-element tools consuming a small fraction of the time ( $1.5\times 10^{-3}$ %), significantly ameliorating the design of ICL-based 3-D-ICs. We also demonstrate that using COIL-3-D to optimize ICL inductor layouts can yield significant performance (up to 41.5% bandwidth improvement) and power (up to 8.1% power improvement) benefits, when compared with layouts used in prior ICL implementations. For these reasons, this paper unlocks new potential for low-cost, power-efficient 3-D integration using ICLs.