Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface

This paper presents practical high-speed and low-power design methodologies for digital PHY in deep sub-micron technologies. The standard-cell-based design approaches with automated place and route shorten the design time dramatically. In addition, robust digital design flow can be applied for wide range of operation considering model-hardware-correlation in deep sub-micron technologies. Eventually, all-digital PHY improves power efficiency of the system with wide-voltage-range DVFS. Simplified architecture with calibration logic helps improve logic speed with minimized area and power. The designed PHY with proposed design methodologies shows 1.6Gbps at 520mV and 6.6Gbps at 780mV, which allows extreme power efficiency and performance. In addition, the wide range of voltage scaling is allowed depending on the target frequency.