Advanced device performance impact by wafer level 3D stacked architecture

A high density 50K∼100K/mm2 cross-tier connection featuring backside through-via (BTV) and wafer level 3D stacking technologies has been successfully demonstrated. Wafer stacking and thinning to < 1/250 Si thickness process showed little to no impact to advanced device performance. BTV induced stress effect was also studied; quite different behaviors between wafers with SiGe and without SiGe process were found. SiGe local strain will be diminished by BTV induced strain when BTV getting too close to channel, and hence lower hole mobility. This impact could be minimized by proper Keep-Out Zone (KOZ) design. Furthermore, 3D stacked architecture provides the opportunity to individually optimize process and design for each function block on separated wafers, thus improve chip performance and power consumption, and also benefit chip footprint.