Process integration and challenges of Through Silicon Via (TSV) on silicon-on insulator (SOI) substrate for 3D heterogeneous applications

Through Silicon Via (TSV) provides an alternative solution to the traditional scaling of Moore's Law. Besides the many advantages including reduction in form factor, higher I/O counts and lower power consumption, TSV also enables 3D heterogeneous integration for various application platforms (e.g. logic, memory, MEMS). For the past decade, silicon-on-insulator (SOI) substrate has been used in RF device fabrication for its low loss property, reducing parasitic loss on the substrate. This paper highlights the demonstration of Cu-filled TSVs on SOI substrate by via-first approach for RF MEMS applications. Process details, issues and challenges will be discussed. Fabricated TSV has a dimension of 20μm × 100μm.