Implementing true random number generators based on high fanout nets

The main component of a true random number generator (TRNG) is its source of entropy. Field Programmable Gate Arrays (FPGAs) are emerging as a popular platform for implementing single-chip TRNGs. Most of the generators implemented in FPGAs exploit the jitter from ring oscillators as source of entropy. The present paper proposes a new method for implementing TRNGs in FPGAs based on high fanout circuits operating at high frequency. The advantage of this design is its solid source of entropy and its high throughput. The quality of the random number stream is further increased by applying post-processing functions. All the theoretical assumptions related to the analysis of the entropy source are validated by practical implementations and results.