Em Noise Immunity Enhancement Using Schmitt Trigger Logic Gates In Cmos Process

The electromagnetic interference (EMI) problem can be resolved in different levels in system design, such as package, circuit and gate level. In this work, we propose and validate a digital logic gate design method to improve EMI performance of digital circuits. We propose one-sided hysteresis dynamic threshold MOSFET (DTMOS) Schmitt Trigger (S. T.) logic gates that can be implemented in standard 0.18 mu m CMOS logic process. In order to overcome the limitation of small hysteresis width, two additional transistors are added in a unit gates structures. The building blocks of digital circuits such as buffer, NAND and NOR gates are fabricated and the hysteresis transfer characteristics are measured and confirmed.