Design of area efficient DDS IP core generator
2015 12th IEEE International Conference on Electronic Measurement & Instruments (ICEMI)(2015)
摘要
This paper introduces an IP core generator software use to generate ROM compressed DDS circuit block for wireless communication system based on linear interpolation DDS architecture. The generated DDS core circuit can effectively reduced waveform ROM size with various output data and frequency turning word bit width configuration. The synthesis result of generated cores on low cost FPGA platform can also support high-speed working clock frequency.
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关键词
DDS,FPGA,Signal Synthesis,IP Generator
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