Vertically Stacked-Nanowires Mosfets In A Replacement Metal Gate Process With Inner Spacer And Sige Source/Drain
2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)(2016)
摘要
We report on vertically stacked horizontal Si NanoWires (NW) p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si p-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs p-FETs.
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关键词
short-channel characteristics,fabrication process,strain fields,PED technique,precession electron diffraction technique,regrown S-D junctions,source-drain stressors,stacked-NW transistors,p-MOSFET,inner spacer,RMG process,replacement metal gate process,vertically stacked-nanowire MOSFET,SiGe
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