A Novel SuperSteep Subthreshold Slope Dual-Channel FET Utilizing a Gate-Controlled Thyristor Mode-Induced Positive Feedback Current
IEEE Transactions on Electron Devices, pp. 1336-1342, 2017.
Logic gatesField effect transistorsJunctionsThyristorsSiliconMore(2+)
For the first time, we experimentally demonstrate an FET with a polycrystalline silicon (poly-Si) device featuring supersteep subthreshold slope (SS) around 20 mV/decade at room temperature. This novel dual-channel device is a three-wordline(WL) transistor fabricated in a poly-Si channel, with p+ source and n+ drain. The outer two WLs ser...More
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