MOSFETs in the VeSTIC process - fabrication and characterization

A method for fabrication of VeSFETs, three-dimensional fin-type MOS transistors is presented. The VeSTIC process was developed and experimentally implemented in ITE. The test devics were manufactured, and their electrical characteristics were measured. Methods for extraction of a set of the VeSFET physical parameters are proposed based on the device compact model. The flat-band voltage, mobility and radius of the slit curvature are extracted from the I-V characteristics of a single device.