A 26-Gb/s 8.1-mW receiver with linear sampling phase detector for data and edge equalization

Yipeng Wang,Zhixin Li,John Zhuang,Charlie Zhi,C. Patrick Yue

2017 Symposium on VLSI Circuits（2017）

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摘要

This paper presents a source-synchronous receiver with a quarter-rate linear sampling phase detector (LSPD) with embedded FFE and DFE. The 1-tap FFE and 1-tap DFE are realized by reusing the data samples generated in the LSPD to minimize power and area overhead. The equalization is applied to both data and edge samples to suppress ISI for improving BER and bit efficiency. The 28-nm CMOS receiver IC achieves error-free operation up to 26 Gb/s with a superior bit efficiency of 0.31 pJ/b while compensating for 14-dB channel loss at 13 GHz.

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关键词

edge equalization,source-synchronous receiver,quarter-rate linear sampling phase detector,LSPD,feed-forward equalizer,FFE,decision feedback equalisers,DFE,intersymbol interference,ISI,bit error rate,BER,CMOS receiver IC,channel loss,power 8.1 mW,size 28 nm,loss 14 dB,frequency 13 GHz

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