Multi DOE Study on 28nm (RF) WLP Package to Investigate BLR Performance of Large WLP Die with 0.35mm Ball Pitch Array

Wafer Level Package (WLP) has become mainstream solution for handheld and mobile applications that require less Printed Circuit Board (PCB) footprint but comes with lots of functionality especially designed for high tier premium smartphones available in the market today. 28nm (RF) WLP is the bleeding edge of technology with regards to smallest transistor available in WLP packages that is in high volume production. The Board Level Reliability (BLR) at this high level of Si node integration is crucial to providing the package solution and needs to be characterized to make it possible to bring up a robust and reliable product to the consumer market. Test Vehicles to characterize and understand the effects of Temp Cycling conditions and Drop Shock conditions of a WLP package with 0.35 mm pitch solder ball and different die sizes have been characterized in recent publications [17,19 ].